多核CPU,Multi-Core CPU
1)Multi-Core CPU多核CPU
1.Use Multi-Core CPU realizes high performance UTM;用多核CPU实现高性能UTM
2.Design and Application of Crossbar Switch Bus in 64-bit Multi-core CPU;64位多核CPU中交叉开关总线的设计与实现
3.Research on niche hybrid genetic algorithm based on multi-core CPU多核CPU环境下小生境混合遗传算法的研究
英文短句/例句

1.Realizing High Performance SSL VPN Based on Multicore CPU;利用多核CPU实现高性能SSL VPN
2.Research on parallel genetic algorithm on multi-core CPU多核CPU环境下的并行遗传算法的研究
3.The Application Research of Parallel Volume Rendering Based on Multi-Core CPU;基于多核CPU的并行体绘制算法应用研究
4.Research on niche hybrid genetic algorithm based on multi-core CPU多核CPU环境下小生境混合遗传算法的研究
5.The Application Research of Parallel Cone-Beam Reconstruction Algorithm Based on Multi-Core CPU for Micro CT;基于多核CPU的微型CT并行锥束图像重建算法应用研究
6.Research on Parallel Recognition Algorithm for Cluster Structure of Complex Networks Based on Multi-core CPU基于多核CPU的复杂网络簇结构并行识别算法研究
7.MMX(Multi Media eXtension)多媒体扩展(CPU)
8.Design of a CPU Core Compatible with MCS-96;兼容MCS-96系列指令记的CPU核的设计
9.The Implementation of TCP/IP Protocol Based on NiosII Softcore CUP;基于NiosII软核CPU的TCP/IP协议实现
10.The Design of 8-bit Turbo-51 s CPU Soft-core;一款8位Turbo-51的CPU软核的设计
11.CPU Hard Core Design Based on MCS-51 Instruction Set基于MCS-51指令集的CPU硬核设计
12.The Development of a Multi-CPU Measurement and Control Device Based on CAN Bus;基于CAN总线的多CPU测控装置的研制
13.Design for Multi-CPU Hardware System of Power Equipment;用于电力装置的多CPU硬件系统设计
14.Design of Target Identification and Tracking System Based on Multi-CPU基于多CPU的目标识别与跟踪系统设计
15.Design and Realization of CPU Nucleus and Virtual Platform Based on FPGA;基于FPGA的CPU核及其虚拟平台的设计与实现
16.Research of Video Decoding and Display of Digital TV Based on CPU with a MIPS Core;基于MIPS核CPU的数字电视的视频解码和显示研究
17.The Research and Application on Numerical Control System(STAR-NP) Based on Single-chips;多CPU单片机数控系统(STAR-NP)的研究及应用
18.Design and Implementation of the Multi-CPUs Control System Based on RS-485 Bus;基于RS-485总线的多CPU控制系统的设计与实现
相关短句/例句

CPU coreCPU核
1.The system is designed with an analogy circuit module and a C51 CPU core.整体系统设计包括模拟电路模块和C51CPU核。
2.An 8 bit embedded CPU core compatible with Motorola 68HC05 is presented in the paper.介绍了一个与 Motorola68HC0 5指令兼容的 8位 CPU核的设计 ,分析了系统结构和工作原理以及设计构思 ,最后简要介绍了一个用 VHDL语言实现的通用仿真验证软件。
3.An embedded 16-bit RISC CPU core was designed and implemented on FPGA.本文基于FPGA平台设计并实现了一种嵌入式16位RISCCPU核。
3)multi-CPU多CPU
1.Design of multi-CPU-based UPFC control and protection system;基于多CPU的UPFC控制与保护系统设计
2.This design adopts multi-CPU embedded system policy and masterslave CPU hardware structure,which was developed that 89C52 microcontroller(slave CPU) played a role of AC sampling and S3C4510B(master CPU) took responsibility for calculating electric parameter,network communication and system management.以嵌入式技术的广泛应用为背景,探讨了一种基于ARM7和51单片机的嵌入式电能在线监测设备的设计,该装置采用多CPU嵌入式系统设计方案和主从式CPU硬件结构,单片机89C52(从CPU)负责电流电压的交流采样,嵌入式S3C4510B(主CPU)负责电力参数计算、网络通信和系统管理。
3.Using multi-CPU the technology to make the improvement to the isotope measuring appliance technical performance,makes it has the obvious superiority in the parallel processing and the real-time gathering data aspect and could enormously enhance the measuring appliance the.探讨了一种适用于电力、冶金、化工等领域的新型仪表DJ-H多通道主从式核料位计的工作原理和系统结构,利用多CPU的技术对同位素仪表的技术性能进行改进,使其在并行处理和实时采集数据方面具有明显的优势,能极大地提高仪表的稳定性和可靠性。
4)soft-core CPU软核CPU
1.In any specific application of the system on programmable chip(SOPC),the instructions used compose a unique subset of the instruction set of the soft-core CPU.在可编程片上系统(System on P rogramm ab le Ch ip,SOPC)中,特定应用程序中用到的指令是软核CPU指令集的子集,如果在FPGA中实现软核CPU时仅保留应用程序用到的指令子集,将可以提高硬件资源利用率。
5)CPU coreCPU内核
1.This paper introduces the method to realize 1553B bus controller in FPGA, expatiating with emphasis on the method to construct a 32 b CPU core with reduced instructions in FPGA, the design of message generator, and the flow of message generation and process.重点说明了在FPGA中构建一个精简指令的32位CPU内核的方法、消息发生器的设计以及消息发生与处理流程。
2.Through studying 8-bit CPU core and implementing it on FPGA, this paper has made a try on the research and design of SoC.通过对8位增强型CPU内核的研究及其在FPGA(Field Programmable Gate Array)上的实现,对SoC设计作了初步研究。
6)CPU Soft CoreCPU软核
延伸阅读

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